Tesla restarted the Dojo project in January 2026. This project supports the training of Optimus humanoid robots. Optimus requires ten times the compute used for vehicle AI. The training pipeline relies on the D1 chip architecture. Tesla disbanded the Dojo project in August 2025, but the restart aims to advance the company’s physical AI goals.
D1 Chip Architecture and Technical Specifications
The D1 chip uses 7nm semiconductor nodes. It contains 50 billion transistors on a 645mm2 die. Each chip reaches 376 teraflops using BF16 or CFloat8 precision. The training tile packages 25 D1 chips in a 5×5 array. This tile achieves 9 petaflops at BF16 or CFloat8 precision and consumes 15 kilowatts. Each tile supports 36 TB/s of aggregate bandwidth via 40 input/output chips. The 25 D1 chips use 1.25 MB of SRAM per core. There are 354 cores per D1 chip. A full chip reaches 362 TFlops of BF16 or CFP8. The die runs at 2 GHz and totals 440 MB of SRAM.
| Specification | D1 Chip Value | Training Tile Value |
|---|---|---|
| Transistor Count | 50 billion | 1.25 trillion |
| Precision (BF16/CFloat8) | 376 TFLOPS | 9 PFLOPS |
| Precision (FP32) | 22 TFLOPS | 550 TFLOPS |
| SRAM per Unit | 1.25 MB | 11 GB |
| Power Consumption | 400 W | 15 KW |
| Off-chip Bandwidth | 8 TB/s | 36 TB/s |
The D1 instruction set supports both 64-bit scalar and 64-byte single instruction, multiple data vector instructions. The integer unit mixes RISC-V and custom instructions. It supports 8, 16, 32, or 64 bit integers. The custom vector math unit is optimized for machine learning kernels and supports multiple data formats. Up to 16 vector formats can be used simultaneously. Each D1 node uses a 32-byte fetch window and holds up to eight instructions. These instructions go to an eight-wide decoder with two threads per cycle. The system uses a four-wide, four-way SMT scalar scheduler with two integer units and two address units. The vector instructions go to a dedicated vector scheduler with two-way SMT. This scheduler feeds a 64-byte SIMD unit or four 8x8x4 matrix multiplication units.
Memory Constraints and Data Type Requirements
Tesla lacks sufficient memory for massive multi-trillion parameter models. On a single functional unit, the chip has 1.25 MB of SRAM. The 354 units in a mesh per chip do not provide enough on-die memory. This shortage explains why Tesla created the CFloat8 data type to stretch the limited memory. This lack of on-die memory led to poor performance and TCO versus Nvidia for Graphcore. Graphcore has twice the SRAM per die of the D1. The ExaPOD provides only 1.33 TB of total memory for over an exaflop of FP16. This memory constraint forces researchers to optimize models heavily. Researchers must address the SRAM or they risk running very quickly.
The 1.25 MB of SRAM per core is the only large memory structure on the die. The lack of other SRAM structures on the die makes scaling to multi-trillion parameter models difficult. The ExaPOD scale consists of 10 cabinets. Each cabinet contains 12 tiles. This configuration provides 106,200 cores, 3,000 D1 chips, and 132 GB of SRAM. Each tile supports 10 TB/s of on-tile bandwidth. The design relies on a high-speed mesh network to route communications between functional units in one clock cycle.
Packaging, Yield, and Power Management
Tesla uses a fan out wafer process for its training tiles. This packaging uses the TSMC integrated fan out system on wafer. The 25 D1 chips sit in a 5×5 array on a single wafer. This design requires every chip in the 5×5 section to work flawlessly. If one chip fails, the entire tile fails. This requirement creates significant yield risks compared to standard packaging. The custom voltage regulator modulator is reflowed directly onto the fan out wafer. Power comes from the bottom and heat exits through the top. The development of the D1 chip and the Dojo supercomputer requires massive engineering efforts to manage the high power density and the extreme bandwidth requirements of the 25 chip training tiles.
The packaging is expensive, yet it is the only way to reach 8 TB/s of I/O. The interchip bandwidth is high because of the 576 SerDes channels. These channels move 8 TB/s across all four die edges. The high power density means power and thermal management interface directly with the tile. The D1 chip has a thermal design power of approximately 400 watts. The training tile draws 15 kilowatts. Each cabinet in the ExaPOD contains 12 tiles.
The Three-Stage Optimus Learning Pipeline
The Optimus learning pipeline uses three stages. First, the robot performs imitation learning from video. Tesla records humans using a five-camera helmet rig and a backpack sensor pack. The robot studies these demonstrations and reproduces the spatial movements and timing. Second, the robot practices in a simulated environment. Tesla uses video-generation AI models as physics engines to create thousands of synthetic training scenarios. One real demonstration produces 10,000 synthetic variations. This stage helps the robot learn grip adjustments and edge cases. Third, the robot learns through fleet-wide sharing. Once one Optimus robot masters a task, the skill spreads to every other unit.
The training for Optimus relies on an adapted version of the FSD neural network, and improvements in vehicle perception improve the robot’s ability to understand and manipulate complex objects in its environment. Tesla records these human demonstrations through first-person camera rigs. These rigs capture minute details like the location of joints and fingers. The robot uses these inputs to learn motor commands. This approach allows the robot to generalize patterns across many different tasks.
Scaling with Cortex 2.0 and the AI Roadmap
Tesla scaled Cortex 2.0 toward 500 megawatts and 230,000 GPUs by mid-2026. This cluster forms the training backbone for Optimus neural networks. A complete neural network training cycle takes 70,000 GPU hours on Cortex. Optimus uses an adapted version of the FSD neural network. The architecture maps visual input to 78 actuators. The AI5 chip design is stable and supports Optimus. The AI5 chip will make the cars almost perfect and improve Optimus.
Tesla follows a granular silicon roadmap. The AI4 chip serves as the current backbone for vehicles. The AI5 chip focuses on perfecting the driving experience and enhancing Optimus. The AI6 chip focuses on data centers and Optimus. The AI7 chip, which is linked to Dojo 3, serves as space-based AI compute. This roadmap moves from AI4 to AI7 in rapid cycles. Musk stated that AI7, AI8, and AI9 undergo nine-month development cycles.
Data Moats and the Vehicle Fleet
The 8.2 billion miles of real-world driving data from the vehicle fleet provides the foundation for Optimus. This data teaches the robot object recognition, spatial understanding, and depth estimation. The training for Optimus uses the same neural architecture as FSD. Improvements in vehicle perception improve the robot’s ability to understand and manipulate complex objects in its environment. The massive dataset of 1.5 petabytes from the primary GPU cluster helped train the initial Autopilot models. This scale of data is difficult for competitors to replicate.
The training for Optimus relies on an adapted version of the FSD neural network, and improvements in vehicle perception improve the robot’s ability to understand and manipulate complex objects in its environment. The visual processing and spatial awareness built for driving map onto a bipedal body. The robot learns from the most complicated and diverse scenarios in the world. This data comes from millions of vehicles in real time.
Hardware Economics and the Build-vs-Buy Strategy
Tesla builds its own AI training infrastructure to reduce costs. Owning compute is cheaper than renting H100 or B200 clusters from cloud providers if utilization remains high. At 80% utilization over four years, Dojo’s per-PFLOP cost falls below cloud rates. Tesla avoids the risk of a single-vendor supply chain. The NVIDIA H100 shortage demonstrated the danger of relying on one supplier. Dojo provides Tesla with guaranteed compute capacity that scales with production.
The training for Optimus relies on an adaptedwa version of the FSD neural network, and improvements in vehicle perception improve the robot’s ability to understand and manipulate complex objects in its environment. The costs of training Optimus will grow as the robot fleet expands. If Optimus reaches 50,000 units, the data generation rate will increase. Tesla needs to own the compute layer to manage these costs.
Will the custom interconnects maintain these speeds at the full ExaPOD scale?
The development of the D1 chip and the Dojo supercomputer requires massive engineering efforts to manage the high power density and the extreme bandwidth requirements of the 25 chip training tiles. Tesla continues to recruit engineers to solve these technical problems.
