Funding and Leadership in Reno
Positron AI secured $875 million on September 10, 2026. This funding includes a $375 million Series C and a $500 million Series C-1. The total brings the post-money valuation to $5 billion. Mitesh Agrawal leads the company as CEO. He previously managed growth at Lambda, where he helped increase annualized revenue from $500,000 to $500 million. He now leads the mission to deliver domestically made AI compute solutions. Co-founders Thomas Sohmers and Edward Kmett join him. Sohmers is a Thiel Fellow and serves as CTO. Kmett is a mathematician who serves as the Chief Scientist. The founders met as technical leads on Apple’s early Vision Pro team. Alberto T. later co-founded Luma AI as CTO. Lightspeed Venture Partners led both the Seed and Series A stages, which totaled $59 million in combined funding. Other investors in these stages included WndrCo and Amplify Partners. The board includes Forest Baskett, Gavin Baker, Thomas Jermoluk, and Dylan Patel. Investors like NEA, Atreides Management, Valor Equity Partners, Andra Capital, SemiAnalysis Capital, and Jim Clark provide the capital. Other backers include DFJ Growth, Qatar Investment Authority, Hudson River Trading, Cisco Investments, and Naver Ventures.
Asimov Architecture and Memory
The Asimov chip prioritizes memory bandwidth over theoretical compute. Most accelerators maximize FLOPs and treat memory as an afterthought, but Asimov inverts this design. The architecture uses LPDDR5x instead of High Bandwidth Memory to reduce cost and supply chain risk. This choice provides 6x the memory capacity per chip. The chip provides 2.76 TB/s of realized memory bandwidth.
| Spec | Value |
|---|---|
| Memory per chip | 288GB to 2,304GB |
| Realized Bandwidth | 2.76 TB/s |
| Clock Frequency | 2.0 GHz |
| Chip-to-Chip Interconnect | 16 Tbps |
| Max Cluster Size | 16,384 chips |
| Data Types | TF32, BF16, FP16, FP8, NVFP4, INT4 |
Asimov uses a dual-hemisphere architecture. Each hemisphere operates with its own memory subsystem. This allows the system to scale from single chips to Titan systems. The Titan system combines four to eight Asimov chips to target models with over 16 trillion parameters. The chip includes a 512×128 systolic array running at 2 GHz. This array reconfigures dynamically for FFN Matrix-Matrix Multiplication or memory bound Matrix-Vector Multiplication. Dedicated hardware performs softmax, RMSNorm, RoPE, and SwiGLU at line rate. Multiple on-chip ARMv9 64-bit general purpose processor cores handle workload orchestration and provide a programmable escape hatch. PCIe Gen 6 with CXL support delivers 128 GB/s per hemisphere. The chip-to-chip interconnect provides 16 Tbps of direct bandwidth.
Scaling Inference with Atlas
General Compute is purchasing Atlas systems. They also committed to buying Titan systems. The agreement between General Compute and Positron expands the availability of Atlas systems and establishes a clear path toward the next-generation Titan platform, which targets much larger models than the current GPU-based solutions available on the market. General Compute finances, deploys, and operates purpose-built inference silicon and sells the result as dedicated inference capacity under one contract and one set of SLAs. This company recently announced a $400 million debt facility from Upper90. The Atlas deployment involves networking and security validation, rack integration, and power and cooling constraints. This work alongside Oracle Cloud Infrastructure provides the necessary validation for high-scale production. Atlas is currently in more than 50 racks at Oracle Cloud Infrastructure. Other customers include Parasail, Jump Trading, and i3d.net. The Atlas deployment uses a heterogeneous approach by pairing GPUs for compute-intensive prompt processing with Positron’s memory-first accelerators for token generation. The Atlas system provides 3.5x better performance per dollar and 3.5x greater power efficiency than Nvidia H100 GPUs for inference. It also provides 70% faster inference at 66% lower power consumption than H100 or H200 setups. This slashes data center CapEx by 50%. You already know that HBM supply constraints plague the industry. Positron avoids these issues by using LPDDR5x. I find the company’s claims about the Asimov tape out in late 2026 to be a major risk since they have not yet demonstrated these results. Will the LPDDR5x architecture maintain these performance leads when scaling to the full 16,384 chip cluster?
