The $5 billion valuation and Asimov development
Positron AI raised $875 million in its latest funding round, increasing its valuation to $5 billion. This financing includes a $375 million Series C at a $3.5 billion pre-money valuation and a $500 million Series C-1 led by NEA and Jim Clark. Other investors include Atreides Management, Valor Equity Partners, Andra Capital, SemiAnalysis Capital, Qatar Investment Authority, Cisco Investments, and Naver Ventures. These proceeds fund the final design stage of the Asimov chip and the building of a 2 MW engineering data center. The company targets Asimov production in the second half of 2027. The Titan system combines four to eight Asimov chips to serve models exceeding 16 trillion parameters and context windows beyond 10 million tokens in a single node using up to two terabytes of high-speed memory per accelerator. Forest Baskett, Gavin Baker, Dylan Patel, and Thomas Jermoluk join the board. This follows a $230 million Series B co-led by ARENA Private Wealth, Jump Trading, and Unless. Total capital raised this year exceeds $75 million. With global tech firms projected to spend over $320 billion on AI infrastructure by 2025, Positron seeks to capture a significant share of the inference market.
Atlas deployment and LPDDR5X efficiency
The company currently deploys over 50 racks of Atlas, its first-generation inference system, at Oracle Cloud Infrastructure. Atlas serves LLM hosting, generative agents, and enterprise copilots. If you follow the supply chain, you know the HBM bottleneck constrains scaling for most firms. Positron bypasses this by using LPDDR5X instead of high-bandwidth memory. Atlas delivers 3.5 times better performance per dollar and 66% lower power consumption than NVIDIA’s H100. It generates 3 times more tokens per watt than existing GPUs. The Atlas architecture uses memory-optimized FPGA to achieve 93% bandwidth utilization. This allows the system to support models with up to half a trillion parameters in a single 2-kilowatt server. The hardware is compatible with Hugging Face transformer models and processes inference requests through an OpenAI API-compatible endpoint. This allows for lower latency and reduced hardware demands. Parasail, Jump Trading, and i3d.net all use Atlas for production.
| Feature | Atlas (First-Gen) | Titan (Next-Gen) |
|---|---|---|
| Architecture | Memory-optimized FPGA | Asimov custom silicon |
| Max Parameters | 0.5 trillion | 16 trillion |
| Context Window | Not specified | > 10 million tokens |
| Memory Type | LPDDR5X | LPDDR5X |
| Memory Capacity | Not specified | Up to 2,304 GB per chip |
Positron previously raised $51.6 million in a Series A round to accelerate second-generation product launches. The company aims to address rising cost pressures and power limits facing businesses today.
Photonic computing and the bandwidth gap
Photonic chips process information using light instead of electrical currents. Research from Saumil Bandyopadhyay demonstrates a single photonic chip capable of running a deep neural network entirely in the optical domain. The chip uses a 220-nm silicon-on-insulator platform and performs linear and nonlinear operations using light. This architecture achieves 92.5% accuracy on a vowel classification task. Data processing occurs in 410 picoseconds at femtojoules per operation. The hardware includes Mach-Zehnder interferometers, thermo-optic phase shifters, and InGaAs single-photon avalanche detectors. The architecture uses forward-only training to adjust weights directly during forward propagation. This method avoids the complex feedback loops required by backpropagation through the use of directional gradients. During training, the system slightly perturbs weights and evaluates the impact on the output through multiple forward passes. This enables training to happen almost as quickly as inference.
Positron’s reliance on LPDDR5X is a massive gamble. Samsung research shows standard LPDDR5X interface bandwidth at 76.8 GB/s, while HBM4 can reach over 2 terabytes per second. The massive throughput gap between LPDDR5X and HBM4 remains an obvious physical barrier. Can the Asimov architecture overcome the massive bandwidth limitations of LPDDR5X for future model scales?




